Multi-bit non-volatile memory device and method therefor

ABSTRACT

A multi-bit non-volatile memory device includes a charge storage layer ( 14 ) sandwiched between two insulating layers ( 12  and  16 ) formed on a semiconductor substrate ( 10 ). A thick oxide layer ( 18 ) is formed over the charge storage layer ( 14 ) and a minimum feature sized hole is etched in the thick oxide layer ( 18 ). An opening is formed in the thick oxide layer ( 18 ). Side-wall spacers ( 60 ) formed on the inside wall of the hole over the charge storage layer have a void ( 62 ) between them that is less than the minimum feature size. The side-wall spacers ( 60 ) function to mask portions of the charge storage layer ( 14 ), when the charge storage layer is etched away, to form the two separate charge storage regions ( 55  and  57 ) under the side-wall spacers ( 60 ). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductor devices,and more particularly, to multi-bit non-volatile memory semiconductordevices and method therefor.

BACKGROUND OF THE INVENTION

[0002] One type of non-volatile memory uses traps in an insulating layerfor charge storage. One material used in such a manner is siliconnitride. Typically, the nitride charge storage layer is surrounded byother insulating layers such as oxide forming an oxide-nitride-oxide(ONO) structure. Charge stored within the nitride is used to manipulatea threshold voltage of the transistor, and in this manner store data. Aconventional non-volatile memory gate cell typically exists in one oftwo states representing either a logical zero or a logical one. Toincrease the capacity of a memory device without significantlyincreasing the size of the memory, a multi-bit memory cell may be usedthat is capable of storing more than two states. Non-volatile memorycells of this type, referred to herein as multi-bit memory cells, havebeen historically implemented by controlling the amount of charge thatis injected into portions of the nitride charge storage layer.

[0003] The reliability of multi-bit memory cells that rely onlocalization of charge is susceptible to charge migration thatdelocalizes the stored charge. More specifically, the charge may migratethrough the nitride layer, causing the stored logic states to change. Inmulti-bit non-volatile memory cells that use multiple independentfloating gates, it has been necessary to use multiple non-self-alignedmasking steps to fabricate the multiple floating gates, significantlyincreasing the cost of the device due to the increased processcomplexity and larger size of the memory cell.

[0004] Therefore, there is a need for a multi-bit non-volatile memorydevice having good data retention capabilities while also beinginexpensive to manufacture.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1-FIG. 9 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with afirst embodiment of the present invention.

[0006]FIG. 10-FIG. 17 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with asecond embodiment of the present invention.

[0007]FIG. 18-FIG. 24 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with athird embodiment of the present invention.

[0008]FIG. 25-FIG. 31 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with afourth embodiment of the present invention.

[0009]FIG. 32-FIG. 36 illustrates, in cross-sectional views, a methodfor forming a multi-bit non-volatile memory device in accordance with afifth embodiment of the present invention.

DETAILED DESCRIPTION

[0010] Generally, the present invention provides a multi-bitnon-volatile memory device having a charge storage layer sandwichedbetween two insulating layers. The charge storage layer typicallyincludes nitride, nanocrystals, or polysilicon, although metallicmaterials or other materials that contain traps may be employed as thecharge storage layer. In one embodiment, a thick oxide layer is formedover the charge storage layer and a minimum feature size hole is etchedin the thick oxide layer. Two charge storage regions, each of which maystore an independent bit, are formed in the charge storage layer. Anopening is formed in the thick oxide layer. Side-wall spacers formed onthe inside wall of the opening over the charge storage layer have adimension in one direction that is less than a minimum feature size. Theside-wall spacers function to mask portions of the charge storage layerwhen the charge storage layer is etched away to form two separate chargestorage regions under the side-wall spacers. Separating the chargestorage regions prevents lateral conduction of charge from one bit toanother. Also, using side-wall spacers to pattern the charge storagelayer allows the resulting device to be self-aligned so that only onephoto masking step is needed to form the device.

[0011]FIG. 1-FIG. 9 illustrate cross-sectional views of steps forforming a multi-bit non-volatile memory device in accordance with afirst embodiment of the present invention. FIG. 1 illustrates across-sectional view of a structure formed on a substrate 10. Adielectric stack is formed over substrate 10 and includes insulatinglayer 12, charge storage layer 14, and insulating layer 16. In theillustrated embodiment, insulating layer 12 is grown from substrate 10.Insulating layer 16 is deposited on charge storage layer 14. In oneembodiment, insulating layer 16 is a deposited oxide layer. Chargestorage layer 14 includes a plurality of discrete charge storageelements. In the illustrated embodiment, nanocrystals, represented bythe small circles in charge storage layer 14, are used to form theplurality of discrete charge storage elements. These nanocrystals aretypically formed of silicon, but the discrete storage elements may alsobe formed of clusters of material consisting, for example, of germanium,silicon carbide, any number of metals, or any combination of these FIG.2 illustrates a cross-sectional view of the multi-bit non-volatilememory device after a hard mask layer 18 is deposited on insulatinglayer 16. Photo resist layer 20 is deposited over insulating layer 18and then patterned. Layer 18 is then etched in the areas not covered bypatterned photo resist layer 20. Layer 18 is typically oxide, but may beany number of materials that is etch selective to the spacer and gatematerials that will be used.

[0012]FIG. 3 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after photo resist layer 20 is removed andside-wall spacers 22 are subsequently formed over oxide layer 16.Typically, the side-wall spacers are formed by deposition of a layer ofspacer material, followed by an anisotropic etch of the spacer material.The spacer material is typically nitride, although it may be formed ofany other material for which there is a selective etch between it andlayer 16 and 14. FIG. 4 illustrates a cross-sectional view of themulti-bit non-volatile memory device after insulating layers 12 and 16and charge storage layer 14 are etched away to form a void 24 betweenside-wall spacers 22.

[0013]FIG. 5 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after an oxide layer 26 is thermally grown invoid 24 between side-wall spacers 22 from substrate 10. The use ofthermally grown oxide results in better memory bit drive current due toimproved mobility as compared to deposited oxide. Oxide layer 26 isbetween about 15 angstroms to 30 angstroms in thickness in theillustrated embodiment. In other embodiments, oxide layer 26 may have adifferent thickness. Two charge storage areas are formed in chargestorage layer 14 on both sides of void 24.

[0014]FIG. 6 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after side-wall spacers 22 are removed.

[0015]FIG. 7 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after a gate material 28 is formed over oxidelayers 18 and 26. In the illustrated embodiment, gate material 28 isdeposited polysilicon. In other embodiments, the gate material may bedeposited metal or other materials used for forming gate electrodes.

[0016]FIG. 8 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after a top portion of gate material 28 isremoved to form a gate 30. The material is removed using chemicalmechanical polishing (CMP) in the illustrated embodiment.

[0017]FIG. 9 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after etching insulating layer 18. Also, aportion of insulating layers 12 and 16 and charge storage layer 14 areremoved forming charge storage portions 33 and 35. Most of insulatinglayers 12 and 16 and charge storage layer 14 are etched away except forthat portion remaining under gate electrode 30, with gate electrode 30functioning as a masking layer. Side-wall spacers 32 are then depositedon the sides of gate electrode 30 and charge storage portions 33 and 35.In the illustrated embodiment, side-wall spacers 32 are formed fromnitride. After forming side-wall spacers 32, drain/source regions 34 and36 are diffused into substrate 10. Note that drain/source regions 34 and36 and side-wall spacers 32 are formed using conventional semiconductorprocessing techniques. Note also that drain/source regions 34 and 36 mayinclude drain/source extensions under the side-wall spacers 32.

[0018] The resulting multi-bit non-volatile memory device illustrated inFIG. 9 can separately store charge, representing a logic state, oneither charge storage region 33 or charge storage region 35. Arelatively thin oxide layer 26 improves transistor performance byincreasing drain/source current carrying ability. Also, etching betweencharge storage regions 33 and 35 provides better charge retention bybetter isolating the two charge storage regions.

[0019] To program, for example, charge storage region 35, a programmingvoltage is applied to gate 30 and drain/source region 36 whiledrain/source region 34 is held at ground potential. Charge is theninjected into charge storage region 35. Likewise, to program chargestorage region 33, a programming voltage is applied to gate 30 anddrain/source region 34 while drain/source region 36 is held at groundpotential.

[0020] The device can be read in several ways by measuring the currentpassing from source to drain or from drain to source. Typically, thedevice is read in the opposite direction from which it is programmed.That is, the functions of the drain/source regions are reversed.

[0021] To erase charge storage region 35, an erase voltage is applied togate 30 and drain/source region 36. To erase charge storage region 33,an erase voltage is applied to gate 30 and drain/source region 34.

[0022] Because the charge storage regions are separated, the program anderase operations are simpler to control, since they need not injectcharge into precisely the same physical region, as long as each regionof charge injection extends past the selected charge storage region, butnot to the unselected region on the other side of the device. The chargestorage regions may be more easily returned to the selected erase orprogrammed state after any sequence of such operations than if thecharge storage region were a continuous film, for which the extent ofthe injection regions must be precisely controlled.

[0023]FIG. 10-FIG. 17 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with asecond embodiment of the present invention.

[0024]FIG. 10 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after an ONO structure is formed on substrate50. The ONO structure includes insulating layers 56 and 59 and nitridelayer 58. Insulating layer 56 is oxide grown from substrate 50.Depositing nitride on insulating layer 56 forms charge storage layer 58.Alternatively, any number of dielectric materials, such as aluminumoxide, zirconium oxide, hafnium oxide, tantalum oxide, lanthanum oxide,hafnium silicate, or hafnium aluminate, which contain traps may be usedto form the charge storage layer 58. Insulating layer 59 is deposited onnitride layer 58 or grown by oxidation of nitride layer 58. A hard masklayer 52 is then deposited on insulating layer 59. Typically layer 52 isformed of nitride, but may be any material that is etch selective to thegate and spacer material below. Photo resist layer 54 is deposited oninsulating layer 52 then patterned. Insulating layer 52 is then etched.Note that patterning photo resist layer 54 is the only step requiringthe use of a photomask.

[0025]FIG. 11 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after insulating layer 59 is etched away.Side-wall spacers 60 are then formed by depositing oxide over chargestorage layer 58.

[0026]FIG. 12 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after charge storage layer 58 is removedbetween side-wall spacers 60 to form a void 62 over insulating layer 56.In the process of removing the center portion of charge storage layer58, a portion of insulating layer 52 is also removed. Portions 55 and 57of charge storage layer 58 remain under each of the side-wall spacers60. 5 FIG. 13 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after side-wall spacers 60 and insulatinglayer 56 are etched away forming void 64.

[0027]FIG. 14 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after insulating layer 66 is formed in void64. Insulating layer 66 is formed by growing oxide on substrate 50.Insulating layer 68 is formed by depositing oxide over the entire deviceincluding oxide layer 52 and insulating layer 66.

[0028]FIG. 15 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after gate material 70 is deposited overinsulating layer 68. Gate material 70 is formed from polysilicon in theillustrated embodiment. In other embodiments, gate material 70 may beformed from metal, or the like.

[0029]FIG. 16 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after being planarized. In the illustratedembodiment, the device is planarized using chemical mechanical polishing(CMP).

[0030]FIG. 17 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after insulating layer 52 is removed andside-wall spacers 74 are formed. Drain/source regions 76 and 78 are thenimplanted in substrate 50.

[0031] The resulting multi-bit non-volatile memory device can separatelystore charge, representing a logic state, on either of the chargestorage regions 55 and 57. Alternatively, both charge regions may beused to store a single, redundant bit. A relatively thin oxide layer 66improves transistor performance by increasing drain/source currentcarrying ability. Also, etching the nitride between charge storageregions 55 and 57 provides better charge retention by better isolatingthe two charge storage regions.

[0032] To program, for example, charge storage region 57, a programmingvoltage is applied to gate 70 and drain/source region 78 whiledrain/source region 76 is held at ground potential. Charge is injectedinto charge storage region 57. Likewise, to program charge storageregion 55, a programming voltage is applied to gate 70 and drain/sourceregion 76 while drain/source region 78 is held at ground potential.

[0033] The device can be read in several ways including measuring thecurrent that passes from source to drain or drain to source. Typically,the device is read in the opposite direction from which it isprogrammed. That is, the functions of the drain/source regions arereversed. To erase charge storage region 57, an erase voltage is appliedto gate 70 and drain/source region 78. To erase charge storage region55, an erase voltage is applied to gate 70 and drain/source region 76.The device has the same benefit of simpler control of the erased andprogram states as described above.

[0034]FIG. 18-FIG. 24 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with athird embodiment of the present invention.

[0035]FIG. 18 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after hard mask layer 92 is deposited oversubstrate 90. Layer 92 typically consists of oxide, although anymaterial that is etch selective to the gate and spacer material may beused. Photo resist layer 94 is then deposited on insulating layer 92.Photo resist layer 94 is then patterned. Layer 92 is then removed in theareas devoid of photo resist. Note that the patterning of photo resistlayer 94 is the only step requiring the use of a photomask in a processto form a multi-bit non-volatile memory device in accordance with thepresent invention.

[0036]FIG. 19 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after insulating layer 96 is formed onsubstrate 90. Insulating layer 96 is formed by growing oxide onsubstrate 90. Side-wall spacers 98 are formed by depositing a layer ofcharge storage material over layer 96, followed by an anisotropic etchof the charge storage material. Typically, the charge storage materialconsists of nitride, although any number of dielectrics containing trapsmay be used, such as aluminum oxide, zirconium oxide, hafnium oxide,tantalum oxide, lanthanum oxide, hafnium silicate, or hafnium aluminate.The thickness of layer 96 in the area between side-wall spacers 98 mayoptionally be adjusted by etching and/or regrowing the portion of layer96.

[0037]FIG. 20 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after a portion of side-wall spacers 98 areetched, leaving charge storage regions 100 and 102.

[0038]FIG. 21 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after insulating layer 104 is deposited overinsulating layer 92, charge storage portions 100 and 102, and insulatinglayer 96.

[0039]FIG. 22 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after gate material 106 is deposited. In theillustrated embodiment, gate material 106 is polysilicon. In otherembodiments, gate material 106 may be formed from metal, or the like.

[0040]FIG. 23 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after gate material 106 is planarized,removing most or all of insulating layer 104.

[0041]FIG. 24 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after layer 92 is removed by an etch that isselective to the gate 106, drain/source regions 112 and 114 are diffusedinto substrate 90, and side-wall spacers 110 are formed.

[0042] The resulting embodiment illustrated in FIG. 24 provides the sameadvantages as the previously described embodiments. Charge storagelayers 100 and 102 may be more difficult to form because the selectiveremoval of nitride side-wall spacers 98 may be difficult to controlacross a semiconductor wafer.

[0043]FIG. 25-FIG. 31 illustrate, in cross-sectional views, a method forforming a multi-bit non-volatile memory device in accordance with afourth embodiment of the present invention.

[0044]FIG. 25 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after an ONO (oxide-nitride-oxide) structureis formed on substrate 130. The ONO structure includes insulating layers132 and 136 and charge storage layer 134. While layer 134 typicallyconsists of nitride, any number of dielectrics containing traps may beused, such as aluminum oxide, zirconium oxide, hafnium oxide, tantalumoxide, lanthanum oxide, hafnium silicate, or hafnium aluminate.Insulating layer 132 is grown on substrate 130. Charge storage layer 134is formed by depositing nitride on insulating layer 132. Insulatinglayer 136 is formed by depositing oxide on charge storage layer 134 orgrown by oxidation of nitride layer 134.

[0045]FIG. 26 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after hard mask layer 138 is deposited overinsulating layer 136. Photoresist layer 140 is deposited on insulatinglayer 138 and then patterned. Layer 138 is then removed in the areasdevoid of photoresist.

[0046]FIG. 27 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after photoresist 140 is removed andside-wall spacers 142 are formed. Side-wall spacers 142 are formed bydepositing and anisotropically etching polysilicon. Optionally, athreshold voltage adjust 146 may be implanted at this point in theprocess.

[0047]FIG. 28 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after the exposed regions of insulatinglayers 136 and 134 are etched forming void area 148. At the same time, aportion of layer 138 is etched away. Optionally, the thickness of layer148 may be adjusted by etching, or etching and regrowing.

[0048]FIG. 29 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after void area 148 is filled withpolysilicon. Side-wall spacers 142 and the filled polysilicon form gateelectrode 152. In the illustrated embodiment, the device is planarizedusing chemical mechanical polishing (CMP).

[0049]FIG. 30 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after insulating layers 138, and portions of136, and portions of charge storage layer 134 are removed. Portions ofinsulating layer 136 and charge storage layer 134 remain under gateelectrode 152 forming separate charge storage regions 157 and 159. Areoxidation of gate electrode 152 will result in additional oxidationlayers 154 and 156 forming on the side of gate electrode 152. Inaddition, drain/source extensions 158 and 160 are diffused in substrate130.

[0050]FIG. 31 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after side-wall spacers 166 and 168 areformed using nitride. Drain/source regions 162 and 164 are implanted insubstrate 130. Self-aligned silicide layer 170 is formed overdrain/source regions 162 and 164 and over gate electrode 152. Theembodiment of FIG. 31 is programmed, read, and erased in the same manneras given above for the embodiment of FIG. 9.

[0051] Like the above embodiments, this embodiment prevents lateralconduction of charge in the nitride by physically separating the twobits by breaking the nitride in the middle of the device, and allowssimpler control of the program and erased states.

[0052]FIG. 32-FIG. 36 illustrates, in cross-sectional views, a methodfor forming a multi-bit non-volatile memory device in accordance with afifth embodiment of the present invention.

[0053]FIG. 32 illustrates a semiconductor substrate 180 with a thermaloxide layer 182 grown thereon. After growing oxide layer 182, a thicknitride layer 184 deposited, although layer 184 may also consist of anymaterial for which a selective etch to the gate material exists. Thicknitride layer 184 is patterned using photoresist layer 186 to form anopening 185. Like the other embodiments discussed above, opening 185 isa minimum allowed by the manufacturing process used to create featureson an integrated circuit incorporating the multi-bit non-volatile memorydevice.

[0054]FIG. 33 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after photoresist layer 186 has been removedand side-wall spacers 188 formed on each -side of the opening 185.Side-wall spacers 188 are formed by depositing a layer of charge storagematerial, followed by an anisotropic etch of the charge storagematerial. The charge storage material is typically polysilicon, althougha metallic material may also be used. Side-wall spacers 188 function asthe charge storage structures for the multi-bit non-volatile memorydevice of this embodiment. Optionally, side-wall spacers 188 may beetched to adjust their size. Optionally, oxide layer 182 may be etched,or etched and regrown, to reduce its thickness providing bettertransistor performance as described above. After side-wall spacers 188are formed, oxide layer 190 is formed by either oxidizing polysiliconside wall spacers 188 and substrate 180, or by depositing oxide overside wall spacers 188 and substrate 180 between side-wall spacers 188.

[0055]FIG. 34 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after opening 185 is filled with polysilicongate material 192 or other gate material.

[0056]FIG. 35 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after polysilicon gate material 192 isplanarized forming gate electrode 194. The material is planarized usingchemical mechanical polishing (CMP)

[0057]FIG. 36 illustrates a cross-sectional view of the multi-bitnon-volatile memory device after thick nitride layer 184 is removed andside-wall spacers 200 are formed. The side-wall spacers 200 typicallyconsist of nitride or oxide. Drain/source regions 196 and 198 areimplanted in substrate 180. Note that drain/source regions 196 and 198and side-wall spacers 200 are formed using conventional semiconductorprocessing techniques. Like the embodiments discussed above, themulti-bit non-volatile memory device may be manufactured using only oneself-aligned masking step, thus reducing manufacturing costs.

[0058] The embodiment of FIG. 36 is programmed, read, and erased in thesame manner as given above for the embodiment of FIG. 9. In addition,both of the charge storage regions 188 may optionally be erased at thesame time by application an erase voltage on gate 194, while substrate180 is grounded and source/drain regions 196 and 198 are allowed tofloat.

[0059] A device constructed according to the above disclosed embodimentsof the present invention can be scaled, or reduced in size, because theisolation area between the charge storage regions is smaller than theminimum feature size of the integrated circuit as determined by theside-wall spacers.

[0060] While the invention has been described in the context of apreferred embodiment, it will be apparent to those skilled in the artthat the present invention may be modified in numerous ways and mayassume many embodiments other than that specifically set out anddescribed above. Accordingly, it is intended by the appended claims tocover all modifications of the invention which fall within the truescope of the invention.

What is claimed is:
 1. A method of making a memory device, the methodcomprising: forming a layer of material over the substrate, the layer ofmaterial is etch selective to a gate material; forming an opening in thelayer of material; forming a first charge storage structure and a secondcharge storage structure, the first charge storage structure and thesecond charge storage structure formed by etching a layer of chargestorage material through the opening to form an opening in the layer ofcharge storage material, wherein a first charge storage structureincludes at least a portion of the layer of the charge storage materialremaining after the etching and located on a first side of the openingin the layer of charge storage material and wherein a second chargestorage structure includes at least a portion of the layer of the chargestorage material remaining after the etching and located on a secondside of the opening in the layer of charge storage material; forming agate, wherein the forming the gate includes depositing the gate materialin the opening in the layer of material to form at least a portion ofthe gate, wherein the portion of the gate includes a portion locatedover at least a portion of the first charge storage structure and overat least a portion of the second charge storage structure.
 2. The methodof claim 1 wherein a first side of the opening of the charge storagelayer is aligned with a first side of the opening in the layer ofmaterial and the second side of the opening in the charge storing layeris aligned with a second side of the opening in the layer of material.3. The method of claim 1 further comprising: forming a first spacer inthe opening in the layer of material; forming a second spacer in theopening in the layer of material located apart from the first spacer bya space.
 4. The method of claim 3 wherein the etching the layer ofcharge storage material further includes etching the layer of chargestorage material through the space between the first spacer and thesecond spacer.
 5. The method of claim 3 wherein the first spacer and thesecond spacer are formed from the layer of charge storing material. 6.The method of claim 3 further comprising: wherein the first spacer is aside wall spacer formed on a first side of the opening in the layer ofmaterial and the second spacer is a side wall spacer formed on thesecond side of the opening in the layer of material.
 7. The method ofclaim 3 further comprising: implanting a dopant into the substratethrough the space between the spacers to adjust a threshold voltage ofthe memory device.
 8. The method of claim 3 wherein the first and secondspacers include oxide.
 9. The method of claim 3 wherein the first andsecond spacers include nitride.
 10. The method of claim 3 wherein thefirst and second spacers include polysilicon.
 11. The method of claim 10wherein the gate includes at least a portion of the first spacer and atleast a portion of the second spacer.
 12. The method of claim 3 furthercomprising: removing the first and second spacers after etching thelayer of storage material.
 13. The method of claim 3 wherein the etchingthe layer of the charge storage material through the opening includesetching the first spacer and the second spacer to reduce the firstspacer and the second spacer to form the first charge storage structureand the second charge structure respectively, wherein the first chargestorage structure is made from the first spacer and the second chargestorage structure is made from the second spacer.
 14. The method ofclaim 3 wherein: the spacers are formed over the layer of charge storagematerial; the first charge storage structure includes at least a portionof the layer of charge storing material located under the first spacer;the second charge storage structure includes at least a portion of thelayer of charge storing material located under the second spacer. 15.The method of claim 3 wherein the forming the first and second spacersfurther includes: depositing a layer of spacer material comformally overthe substrate; anisotropically etching the layer of spacer material. 16.The method of claim 1 wherein the layer of charge storage materialincludes nitride.
 17. The method of claim 1 wherein the layer of chargestorage material includes a plurality of discrete charge storageelements.
 18. The method of claim 17 wherein each of the discrete chargestorage elements includes clusters that include at least one of silicon,germanium, silicon carbide, and a metal.
 19. The method of claim 1wherein the layer of charge storage material includes at least one ofhafnium oxide, tantalum oxide, aluminum oxide, zirconium oxide, hafniumsilicate, lanthanum oxide, and hafnium aluminate.
 20. The method ofclaim 1 further comprising: forming a first layer of oxide over thesemiconductor substrate; forming a second layer of oxide over thesemiconductor substrate and over the first layer of oxide, wherein alayer of charge storage material is located between the first layer ofoxide and the second layer of oxide; etching the second layer of oxidethrough the opening in the layer of material to form an opening in thesecond layer, wherein etching the layer of charge storage materialincludes etching the layer charge storage material through the openingin the second oxide layer.
 21. The method of claim 20 furthercomprising: etching the first layer of oxide through the opening in thesecond layer and through the opening in the layer of charge storingmaterial to form on opening in the first layer.
 22. The method of claim21 further comprising: forming oxide in the opening in the first layer.23. The method of claim 1 wherein the layer of material is a dielectricmaterial.
 24. The method of claim 1 wherein the layer of charge storagematerial is formed before a formation of the layer of material.
 25. Themethod of claim 1 wherein the layer of charge storage material is formedafter the formation of the layer of material.
 26. The method of claim 1wherein the layer of material includes oxide.
 27. The method of claim 1wherein the layer of material includes nitride.
 28. The method of claim1 further comprising: removing the layer of material after depositingthe gate material.
 29. The method of claim 28 wherein the forming thefirst charge storage structure and the second charge storage structurefurther includes: etching the layer of charge storing material to removeportions of the layer of charge storing material located under the layerof material that is removed after depositing the gate material.
 30. Themethod of claim 1 wherein the opening in the layer of material is formedby patterning the layer of material to form the opening.
 31. A memorydevice comprising: a substrate; a gate located over the substrate; afirst charge storage structure located over an insulating layer on thesubstrate, at least a portion of the first charge structure locatedunder a first portion of the gate, a second charge storage structurelocated over the substrate, at least a portion of the second chargestorage structure located under a second portion of the gate, the secondcharge storage structure is located apart from the first charge storagestructure. wherein the gate includes a third portion located between thefirst portion of the gate and the second portion of the gate; a gatedielectric, a first portion of the gate dielectric located between thesubstrate and the first charge storage structure, a second portion ofthe gate dielectric located between the substrate and the second chargestorage structure, a third portion of the gate dielectric locatedbetween the substrate and the third portion of the gate, wherein thethird portion of the gate dielectric at a location where the gate isclosest to the substrate, has a thickness that is different from athickness of first portion of the gate dielectric and a thickness of thesecond portion of the gate dielectric.
 32. The memory device of claim 31wherein the thickness of the third portion of the gate dielectric at thelocation is less than the thickness of the first portion of the gatedielectric and less than the thickness of the second portion of the gatedielectric.
 33. The memory device of claim 31 wherein the thickness ofthe third portion of the gate dielectric at the location is greater thanthe thickness of the first portion of the gate dielectric and is greaterthan the thickness of the second portion of the gate dielectric.
 34. Thememory device of claim 31 wherein the first charge storage structure andthe second charge storage structure each include a plurality of discretecharge storage elements.
 35. The memory device of claim 31 wherein awidth of the first charge storing structure and a width of the secondcharge storing structure is less than a minimum feature size.
 36. Thedevice of claim 31 wherein each of the first and second charge storagestructures is for storing one bit of information.
 37. A method of makinga memory device, the method comprising: forming a layer of material overthe substrate and over a layer of charge storage material; patterning anopening in the layer of material; forming a first side-wall spacer on afirst side of the opening over the layer of charge storage material;forming a second side-wall spacer on a second side of the opening overthe layer of charge storage material, the first side wall spacer spacedapart from the second side-wall spacer by a space; forming a firstcharge storage structure and a second charge storage structure, theforming the first charge storage structure and the second charge storagestructure includes etching the layer of the charge storage materialthrough the space between the first side- wall spacer and the secondside-wall spacer to form an opening in the layer of charge storagematerial, wherein a first charge storage structure includes at least aportion of the layer of the charge storage material located under thefirst side-wall spacer and remaining after the etching and a secondcharge storage structure includes at least a portion of the layer of thecharge storage material located under the second side-wall spacer andremaining after the etching; forming a gate, wherein the gate includes aportion located over at least a portion of the first charge storagestructure and a portion located over at least a portion of the secondcharge storage structure.
 38. The method of claim 37 wherein the gateincludes at least a portion of the first spacer and at least a portionof the second spacer.
 39. The method of claim 37 further wherein theforming the gate further includes depositing a gate material in theopening in the layer of material, the method further comprising:removing the layer of material after depositing the gate material;wherein the forming the first charge storage structure and the secondcharge storage structure further includes etching the layer of chargestoring material to remove portions of the layer of charge storingmaterial located under the layer of material removed that is removedafter depositing the gate material.